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Rehenuma Tarannum

Digital Hardware Engineer, a fresh graduate from LTH with the main concentration in Digital IC design. Six months of work experience at Axis Communications on FPGA implementation as well as hands-on experience on ASIC design flow through academic projects. Career interest in Embedded system, IoT.

Digital IC Design & Implementation Digital ASIC Verification

Programming languages

Languages Experience Rating Last used
VHDL 2 years 4 2019
C 1 years 4 2020
Python 0 years 3 2020
Bash 2 years 4 2020
Shell script 0 years 2 2020

Development tools

Tool Experience Rating Last used
Cadence Virtuoso 0 years 3 2019
Cadence Encounter 0 years 3 2019
Git 1 years 3 2019
GNU Emacs 2 years 4 2020
Xilinx Vivado 2 years 4 2020
Matlab 1 years 3 2018
JIRA 1 years 3 2020

Knowledge & technologies

Tool Experience Rating Last used
Logic Design 2 years 4 2020
FPGA 2 years 4 2020
Linux 2 years 4 2020
LTE 0 years 1 2020
Circuit Theory 0 years 3 2014

Languages

Language Skill level
English Highly proficient
Bengali Native speaker
Swedish Basic communication skills

Education

  • MSc in Embedded Electronics Engineering (2018 - 2020) Lunds Tekniska Högskola(LTH)
  • BSc in Electrical and Electronics Engineering (2010 - 2014) BRAC University, Bangladesh

Courses

Description Days Year
Modern Wireless System- LTE & Beyond 60 2019
Embedded System Design 60 2019
Computer Architecture 60 2019
DSP-Design 60 2019
Introduction to structured VLSI 60 2018
Digital IC Design 60 2018
  1. Has some knowledge of the technology/product.
  2. Has previously used the technology/product but may require a brief introduction or course.
  3. Has used this technology/product in projects before and can get going on his/her own.
  4. Feels very confident with the technology/product.
  5. Is very experienced with the technology/product and can support or educate others in this area.

Projects & Employments

Current & previous projects

Thesis Student at Axis Communications AB, Lund

Project Title: FPGA Implementation of an Anonymization Algorithm. Project aimed: *Illustrating the algorithm and adapting it from the hardware perspective. *RTL hardware design of functional blocks. *Implementation and verification of the hardware in an FPGA board. *Comparing the hardware and software implementation and making new adjustments for different hardware trade-offs.

Technologies: SystemVerilog, Xilinx Vivado, Python, FPGA, Image Processing, Computer Vision

Student(Academic) at Lund University, Lund

Project Title: Risc-V PULPino matrix multiplier accelerator extension Project Objective: *Incorporating a $5x5$ matrix multiplier accelerator block in the processor by setting up an APB-bus communication. *Generating the idea, making ASMD, writing RTL code *Simulating and Synthesising the whole system *Place and route of it.

Technologies: VHDL, QuestaSim, tcl

Student (Academic) at Lund University, Lund

Project Title: Verification on FPGA of Risc-V PULPino matrix multiplier accelerator extension Project Objectives: *Testing the hardware implementation of the RISC-V PULPino Matrix Multiplier accelerator block *Verifying on FPGA and matching the result that was extracted from the software implementation in beforehand in IC-project 1.

Technologies: Xilinx Vivado, Linux, C++

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