Programming languages
| Languages | Experience | Rating | Last used |
|---|---|---|---|
| VHDL | 1 years | 4 | 2026 |
| C | 1 years | 4 | 2026 |
| Java | 1 years | 3 | 2026 |
| Verilog | 1 years | 2 | 2026 |
I completed a vocational higher education programme in FPGA Engineering at AGSTU, including a work placement at ECSolutions in Helsingborg where I integrated a RISC-V soft core with an LPDDR2 memory controller and radar interface on an Intel MAX 10 FPGA.
My goal is to work in FPGA design and gradually move into ASIC design. I enjoy working close to the hardware and want to deepen my skills in HDL design, embedded systems, and low-level C alongside my continued studies at Lund University.
Regarding my studies at Lund University, all practical components are completed and only exams remain, which I plan to finish alongside employment.
| Languages | Experience | Rating | Last used |
|---|---|---|---|
| VHDL | 1 years | 4 | 2026 |
| C | 1 years | 4 | 2026 |
| Java | 1 years | 3 | 2026 |
| Verilog | 1 years | 2 | 2026 |
| Tool | Experience | Rating | Last used |
|---|---|---|---|
| Altera Quartus II | 1 years | 5 | 2026 |
| Platform Designer | 1 years | 5 | 2026 |
| SignalTap | 1 years | 5 | 2026 |
| Nios II | 1 years | 5 | 2026 |
| ModelSim | 1 years | 5 | 2026 |
| Studio 5000 | 1 years | 3 | 2022 |
| Language | Skill level |
|---|---|
| Swedish | Native speaker |
| English | Highly proficient |
| Description | Days | Year |
|---|---|---|
| Computer Programming in Java (LTH) | 90 | 2020 |
| Digital Systems (LTH) | 90 | 2020 |
| Computer Communication (LTH) | 90 | 2020 |
| Circuits and Measurements (LTH) | 90 | 2020 |
| Project in Automation (LTH) | 90 | 2022 |
The project was carried out in collaboration with Endress+Hauser and involved physically connecting and programming a PLC system to demonstrate process control. The system comprised various ControlLogix units with sensors including temperature, flow, and pressure. Sensor readings were displayed on a panel. The PLC controller was programmed in Studio 5000 using Ladder Logic (LD).
In this project a computer system was designed on an FPGA using VHDL. The system consisted of a CPU with ROM, four LEDs, and four 7-segment displays. The computer was a state machine that stepped through four different assembly instructions using the FPGA’s internal clock. Register values and CPU state were shown on the 7-segment displays while the LEDs indicated CPU status.
VERILOG - HDLBITS (Ongoing personal project) Completed Verilog exercises on the HDLBits platform with a focus on port declarations, vectors, bit manipulation, and module hierarchy.
INTERRUPT-DRIVEN SENSOR IN C (Ongoing personal project) Building a bare-metal measurement system on ARM Cortex-M using hardware timers, DMA-driven I2C and interrupt-driven UART. Establishing a professional development workflow with git discipline including automated regression with GitHub Actions CI and systematic testing before flashing to hardware.
SYSTEMVERILOG UART CONTROLLER (Ongoing personal project) Designing a complete UART controller in SystemVerilog with assertions embedded in RTL. Applying Verilator lint, svlint, CDC analysis, timing closure with Vivado and regression Makefile. First project in a structured ASIC learning path covering UVM, formal verification and full SoC design.
Provided technical support for hardware and software, performed troubleshooting of Apple devices, and handled digital purchases.
Investigated the feasibility of replacing a microcontroller (MCU) with an FPGA in a radar-based product. Analysed the existing MCU implementation and its signal chain. Implemented a RISC-V NEORV32 soft core with LPDDR2, UART, SPI, and DRAM on a MAX10 FPGA development board. Also implemented a Cortex-M0 soft core with the same peripheral modules. The top-level file integrating all components was written in VHDL.